1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a data driving circuit for a liquid crystal display wherein data lines of a liquid crystal display panel are driven by a sampled ramp system.
2. Description of the Related Art
Recently, image media have been changed into a system of transmitting digital image signals easy to compress an information, instead of the existent analog image signals, in order to provide a high-resolution picture for a viewer. Accordingly, a liquid crystal display (LCD) as a type of image display device also must be driven with digital image signals instead of the existent analog image signals. To this end, a data driving circuit for the LCD converts the input digital image signals into analog signals and applies them to the liquid crystal display panel in such a manner to be suitable for driving pixels of the liquid crystal display panel requiring analog signals. However, the data driving circuit of digital system has a lot of problems in characteristic and throughput because it requires a greater number of input lines and has more complicated configuration in comparison to a sample/hold system as the existent analog system. Particularly, the data driving circuit of digital system must use digital-to-analog converters having a complex circuit configuration because a pixel data is processed in parallel. Hereinafter, a conventional data driving circuit will be described with reference to the accompanying drawings. In this case, it is assumed that the data driving circuit is driven by usually inputting 6-bit or 8-bit pixel data, but it is driven by inputting 3-bit pixel data for the convenience of explanation.
As shown in FIG. 1, the data driving circuit 20 for the LCD includes a first latch array 22 connected to a data bus 27, and a second latch array 24 and a digital-to-analog (D-A) converter array 26 connected to the first latch array 22 in cascade, so as to drive data lines DL1 to DLn included in a liquid crystal display panel 10. Each of the first and second latch arrays 22 and 24 consists of n latches, each of which has a 3-bit length to input 3-bit pixel data. The n latches included in the first latch array 22 are connected to the output terminal of a shift register 28 to be sequentially driven in accordance with a logical value of an output signal of the shift register 28, thereby sampling a pixel data VD from the data bus 27. The n latches included in the second latch array 24 receive pixel data from the n latches simultaneously to convert the same to the D-A converter array 26. Then, the D-A converter array 26 converts n pixel data from the second latch array 24 into analog signals using a method of sampling a ramp signal and applies the converted n pixel signals to the n data lines DL1 to DLn of the liquid crystal panel 10, respectively. To this end, the D-A converter array 26 consists of n D-A converters, each of which consists of a counter 21 and a sample holder 23. Each counter 21 receives 3-bit pixel data simultaneously to generate a sampling signal having a different pulse width in accordance with a logical value of the 3-bit pixel data. In other words, each counter 21 makes a down-count in accordance with an input clock signal to output a pulse width modulated signal corresponding to a size of the pixel data when the 3-bit pixel data has been set. Each sample holder 23 samples and holds a ramp signal inputted via a ramp signal line 25 in an output signal of the counter 21 to apply the same to the respective data lines DL1 to DLn. The sample and holder 23 consisting of a conventional switching transistor is turned on when an output signal of the counter 21 has a high state to charge a ramp signal RAMP inputted via the ramp signal line 25 in each data line DL1 to DLn. When an output signal of the counter 21 is changed into a low state, the sample holder 23 is turned off to maintain the lamp voltage charged in the data line in a turn-on interval. If such a D-A converter of sampled ramp system is used, it becomes possible to reduce an external voltage for analog to digital conversion by a single ramp signal as well as to obtain a relatively simple circuit configuration and an easy gamma correction, etc.
As described above, the conventional data driving circuit for the LCD includes the D-A converter, that is, the counter 21 and the sample holder 23 for each data line DL1 to DL1 so as to convert digital image data into analog image signals. However, the conventional data driving circuit has a drawback in that, since each counter 21 must load a pixel data and down-count the loaded pixel data to output a pulse width modulated signal proportional to a magnitude of the pixel data, it has a complicated circuit configuration. For instance, the counter 21 corresponding to one data line is configured as shown in FIG. 2. If 3-bit data B0, B1 and B2 have been set to first to third JK flip-flops by a load signal LOAD and an enable signal ENABLE, the counter 21 down-counts the set data value in accordance with a clock signal. Accordingly, when each output signal of the first to third JK flip-flops inputted to an OR gate positioned at an output terminal of the counter 21 becomes a low (0) state, the counter 21 stops its operation and outputs a low state of count signal. As a result, the output signal of the counter 21 becomes a pulse width modulated signal remaining at a high state in proportion to a magnitude of the input pixel data as shown in FIG. 3. For example, if image data of xe2x80x98010xe2x80x99 and xe2x80x98111xe2x80x99 are input, then the counter 21 outputs an output signal CNTo having a high-state pulse width in a time interval counting the input pixel data. Thus, the sample holder 23 charges a ramp signal inputted in a pulse width interval of the counter output signal in the data lines.
Meanwhile, a poly-Si system LCD has better device characteristic than an amorphous-Si system LCD so that a driving circuit can be fabricated on a substrate such as a liquid crystal display panel. Accordingly, the tendency is toward a data driving circuit with a small bulk to integrate the data driving circuit onto the liquid crystal panel for the sake of making a compact panel and a cost reduction of the driving integrated circuit. If the conventional data driving circuit is integrated onto the liquid crystal panel, however, a size of the liquid crystal panel becomes very large due to the complex D-A converters. As a result, the data driving circuit occupies a large area of the liquid crystal panel.
Accordingly, it is an object of the present invention to provide a data driving circuit for a liquid crystal display wherein it has a simplified circuit configuration so that it can be easily integrated onto a liquid crystal display panel.
In order to achieve these and other objects of the invention, a data driving circuit for a liquid crystal display according to an embodiment of the present invention includes data input means for inputting n-bit video data; clock generating means for generating 2n different clock signals; and a digital-to-analog converter array for generating a sampling pulse having a different phase in accordance with a magnitude of the video data from the data input means using the 2n clock signals and sampling an input ramp signal in response to the sampling pulse to apply the sampled ramp signal to each of data lines in a liquid crystal panel.
A data driving circuit for a liquid crystal display according to another embodiment of the present invention includes data input means for inputting n-bit video data; sequence pulse generating means for generating 2n sequence pulses; and a digital-to-analog converter array for generating a sampling pulse having a different phase in accordance with a magnitude of the video data from the data input means using the 2n sequence pulses and sampling an input ramp signal in response to the sampling pulse to apply the sampled ramp signal to each of data lines in a liquid crystal panel.